Method and apparatus for mutual synchronization of ASIC devices

ABSTRACT

A method and apparatus are provided for synchronizing communications between different integrated circuits having different individual clock rates. In accordance with exemplary embodiments of the invention, a common clock signal is provided having a frequency greater than or equal to the highest individual clock rate, and the common clock signal is divided to obtain individual clock signals for the different integrated circuits For each integrated circuit an arrangement including a switching device and an edge-triggered storage member is also provided. The arrangement has an input for receiving signals, for example from the other integrated circuits. The arrangement also has an output connected to an input of the integrated circuit. The common clock signal and the individual clock signal corresponding to the integrated circuit are provided to the arrangement. The switching device in the arrangement alternately connects an input of the edge-triggered storage member to one of the arrangement input and the arrangement output, based on a state of the individual clock signal. An output of the edge-triggered storage member functions as the arrangement output. The common clock signal is provided to an edge trigger of the storage member so that on an edge of the common clock signal, the storage member will store a signal present at the storage member input and then provide the currently stored signal at the storage member output.

The present invention concerns a process and arrangement for the mutualsynchronization of application-specific integrated circuits (ASIC)arranged to communicate with one another.

TECHNICAL BACKGROUND

In the field of telecommunications, inter alia, digital systems arefound which consist of several different application-specific integratedcircuits which often cooperate in such a way that data has to betransmitted between the different circuits.

Each operation or change of state in an integrated circuit is initiatedby a clock signal which can be generated in the circuit or can be inputinto the circuit from a clock disposed externally thereof. It isimportant that the parts of an integrated circuit which areinterdependent or communicate with one another in some way aresynchronized in terms of time. This synchronization is brought about bythe clock signal which has to be distributed such that clock skewbetween clock signals in the different parts of the integrated circuitis minimized.

In the case of a digital system comprising a plurality ofapplication-specific integrated circuits (ASIC), all the changes ofstate or operations in the system are controlled by clock signals whichcorrespond to the circuits and are usually generated locally inconnection with the respective circuit. In the same way as for differentparts of an integrated circuit, it is important that differentintegrated circuits in a digital system are synchronized in terms oftime if these circuits are arranged to exchange data. In the case of asystem with a plurality of integrated circuits cooperating with oneanother there should therefore be correspondance between clock signalsbelonging to respective circuits. If this is not the case, clock skewcan occur between clock signals in the different circuits in the systemwhich leads to problems when data is exchanged therebetween.

U.S. Pat. No. 5,317,601 earlier disclosed a technique for feedingsynchronized clock signals at different frequencies to a number ofdifferent parts of an integrated circuit. A number of synchronized clocksignals are generated and distributed to the different parts of thecircuit. In order to improve control of clock skew between thesesynchronized clock signals a synchronizing signal is also generated andis used as a reference for the clock signal. This synchronizing signalis distributed to the different parts of the integrated circuit. Asynchronizing circuit adapted to each part of the integrated circuitreceives the clock signals and the synchronizing signal.

The synchronizing circuit essentially comprises a multiplexer whichthrough-connects the clock signal to the intended part of the integratedcircuit under the control of the synchronizing signal. Eachsynchronizing circuit therefore synchronizes the respective clock signalaccording to the synchronizing signal.

The known synchronizing circuit consequently overcomes the problem ofreducing skew between synchronizing signals to different parts of anintegrated circuit. However the solution can be inadequate when data isexchanged between these parts.

DESCRIPTION OF THE INVENTION

The object of the present invention is to solve the problem of improvingsynchronization between integrated circuits which communicate with oneanother.

This object is achieved for respective integrated circuits by means ofan arrangement and a process whereby an activating pulse edge in acommon clock signal to an edge-triggered integrated circuit can bedetermined. The integrated circuit is arranged to communicate with atleast one further integrated circuit. Each of the circuits which arearranged to communicate with one another, receives the common clocksignal. The different integrated circuits are also arranged to receivefrequency data in the form of a clock signal which is adapted to therespective circuit and which is used for establishing in the respectiveintegrated circuit an activating pulse edge in the common clock signal.

The arrangement according to the invention comprises a switching deviceand an edge-triggered storage member. The switching device is arrangedto receive a clock signal which is adapted to the integrated circuit andwhich has a lower frequency than the common clock signal. The storagemember is in turn arranged to receive an output signal from theswitching device which can change between a first and a second statedepending on the clock signal adapted to the integrated circuit. In thefist state of the switching device an input signal from a secondintegrated circuit with which the integrated circuit communicates isthrough-connected. In the second state of the switching device an outputsignal from the storage member is fed back through the switching deviceand back to the same storage member.

DESCRIPTION OF THE FIGURES

FIG. 1 shows three application-specific integrated circuits withseparate clock signals;

FIG. 2 shows three application-specific integrated circuits whichreceive a common clock signal;

FIG. 3 shows some examples of clock signals; and

FIG. 4 shows the arrangement according to the invention.

PREFERRED EMBODIMENT

In the following the invention will be explained in greater detail withreference to the Figures and in particular FIGS. 2 and 4, FIG. 2 showinga digital system in the case of which a common clock signal CLK iscoupled into a plurality of application-specific integrated circuitsASIC1, ASIC2, ASIC3, and FIG. 4 showing an arrangement in the case ofwhich an activating pulse edge in the common clock signal CLK can bedetermined for the respective integrated circuit.

FIG. 1 shows a system according to the prior art. The system comprisesmeans 1 for generating a common clock frequency. As the Figure shorts,the clock frequencies φ1, φ2, φ3 adapted to the respective circuit canbe generated from the common clock signal CLK by means of a frequencydivider 2. Each of the application-specific integrated circuits ASIC1,ASIC2, ASIC3 shown in the Figures receives the clock signal φ1, φ2, φ3adapted to the respective circuit. However with the solution shownproblems arise when data has to be exchanged between the integratedcircuits ASIC1, ASIC2, ASIC3. As a result of delays in the frequencydivider 2, for example, differences in synchronization can occur betweenthe clock signals φ1, φ2, φ3 in the respective integrated circuits, i.e.problem with clock skew occur when data is exchanged between thecircuits.

The arrangement according to the invention is intended for clock pulsedistribution according to FIG. 2. A common clock signal CLK is generatedand transmitted to a frequency divider 2 which generates three new clocksignals φ1, φ2, φ3 from the common clock signal CLK. These three newclock signals are adapted to the requirement in the respectiveapplication-specific integrated circuit ASIC1, ASIC2, ASIC3. Howevereach of the application-specific integrated circuits also receives thecommon clock signal CLK which is transmitted with a minimum relativedelay to each of the integrated circuits. Each integrated circuit ASIC1,ASIC2, ASIC3 thus receives two different clock signals at differentfrequencies. The integrated circuits are arranged to communicate withone other, which is shown in the Figures by the connection from each ofthe circuits to a common databus 3.

FIG. 3 shows an example of a common clock signal CLK, a first clocksignal φ1 which is adapted to a first integrated circuit ASIC1 and asecond clock signal φ2 which is adapted to a second integrated circuitASIC2. The first and second clock signals φ1, φ2 are generated from thecommon clock signal CLK. The Figure shows the situation at the input ofthe first integrated circuit ASIC1 and at the input of the secondintegrated circuit ASIC2. As the Figure clearly shows, a given delay hasoccurred in the first clock signal φ1 and in the second clock signal φ2in relation to the common clock signal CLK. Both the first and thesecond clock signals are consequently phase-shifted relative to thecommon clock signal CLK. A given delay has also occurred between thefirst clock signal φ1 and the second clock signal φ2, even though thisdelay is considerably shorter in the case shown. In spite of the factthat the delay is relatively short, this clock skew can give rise toproblems when the first and second integrated circuits communicate witheach other. It is therefore advantageous to attempt to reduce the clockskew between the clock signals φ1, φ2 in these two circuits wheneverdata is exchanged.

FIG. 4 shows the arrangement according to the invention. Thisarrangement enables the synchronization of each application-specificintegrated circuit ASIC1, ASIC2, ASIC3 to be adapted to the common clocksignal CLK. Each input of data into a first integrated circuit ASIC1 isthereby performed synchronously with the common clock signal CLK inspite of the fact that the circuit is controlled by a first clock signalφ1 which has a first clock frequency.

A switching device 5 receives the first clock signal φ1 and is actuatedthereby such that it changes between a first and a second state. Thischange occurs for each edge of a clock pulse in the first clock signalφ1 adapted to the circuit such that the switching device 5 is in thefirst state for the entire clock pulse, i.e. the period of time betweena positive edge and a negative edge following the latter in the firstclock signal φ1.

In the first state of the switching device 5 new data is input at theinput of the arrangement 4. This means that an input signal IN to thearrangement 4 is coupled unaffected through the switching device. Theinput signal IN shown in the Figure corresponds to a signal from forexample the second integrated circuit which is controlled by the secondclock signal φ2.

A storage member 6 is arranged for the intermediate storage of the inputsignal IN. The changes of state of the storage member 6 are controlledby the common clock signal CLK which means that input into and outputfrom the storage member 6 occurs at a higher frequency than the inputinto the switching device 5. The storage member 6 receives the outputsignal from the switching device 5 during a first clock pulse and thissignal can already be received at the output of the storage member 6during the same clock pulse. The storage member is arranged to store theinput signal until a new input occurs during a subsequent clock pulse.Consequently intermediate storage occurs during a clock cycle in thecommon clock signal CLK.

During an intermediate period before a nets clock pulse is received inthe first clock signal φ1 it is important that the output signal OUTfrom the arrangement 4 to the first integrated circuit ASIC1 remainsconstant. The integrated circuit ASIC1 triggers on the positive edge ofa clock pulse in known manner in the first clock signal φ1 and theoutput signal OUT of the arrangement should therefore not be changedbefore a new clock pulse is received in the first clock signal φ1. Inorder to enable an unchanged output signal to be output during aplurality of clock cycles in the common clock signal, the output signalfrom the storage member 6 is fed back to the switching device 5. Whenthe switching device 5 changes to the second state, the fed-back outputsignal is through-connected to the storage member 6 which during thesubsequent clock pulse in the common clock signal CLK, through-connectsthe same signal to the storage member output, which signal constitutesthe output signal from the arrangement.

When a new clock pulse is received in the first clock signal, theswitching device returns to the first state again and an input signal tothe circuit can be fed through the switching device to the storagemember. This input signal can then be fed further, by furthersynchronization, to the integrated circuit from the storage member.

For the second integrated circuit ASIC2 shown in FIG. 2 the frequencyfor the second clock signal φ2 is precisely one quarter of the frequencyfor the common clock signal CLK. The use of the arrangement 4 accordingto the invention in the second integrated circuit ASIC2 thus means thatdata from some other integrated circuit ASIC1, ASIC3 can be coupledthrough the switching device 5 during the first clock pulse in thesecond clock signal φ2. The output signal OUT from the arrangement 4.i.e. from the storage member 6, responds to the input signal IN asquickly as the next positive edge is detected in the common clock signalCLK. By means of this clock pulse in the second clock signal φ2 anactivating pulse edge is therefore selected in the common clock signalCLK. During the following three clock pulses of the common clock signalCLK the output signal from the storage member 6 is fed back through theswitching device, which means that the output signal OUT from thearrangement 4 remains unchanged during these pulses. The output signalOUT therefore remains unchanged during the total four clock pulses fromthe common clock signal CLK. A new input signal IN is input into theswitching device 5 when a clock pulse is again received from the otherclock signal φ2. This new input signal IN is processed as indicatedabove.

The arrangement according to the invention and shown in FIG. 4 isarranged for connection to an input on each of the integrated circuitsASIC1, ASIC2, ASIC3 which are arranged to communicate with one other. Bymeans of the arrangement 4 according to the invention a clock signaladapted to the circuit is synchronized with a clock signal CLK which iscommon to all the communicating integrated circuits ASIC1, ASIC2, ASIC3.The output signal OUT from the arrangement 4 according to the inventionconstitutes the input signal to the corresponding integrated circuit.

I claim:
 1. Arrangement for determining a first activating pulse edge ofa common clock signal wherein the first activating pulse edge enables afirst edge-triggered integrated circuit to communicate with at least asecond edge-triggered integrated circuit, comprising:a switching devicewhich is arranged to receive frequency data in the form of a first clocksignal which is applied to the first integrated circuit and has a lowerfrequency than the frequency of the common clock signal; and a storagemember, which is edge-triggered by the common clock signal and isarranged to receive an output signal from the switching device and toprovide an output signal from the arrangement to the firstedge-triggered integrated circuit; wherein the switching device isarranged to change between a first state and a second state by changingits state dependent on the first clock signal, wherein, in the firststate, an input signal from the at least second integrated circuit isthrough-connected to the storage member and, the second state, theoutput signal from the storage member is fed back to the storage member.2. Arrangement according to claim 1, wherein the storage member isarranged to trigger on a positive edge of the common clock signal. 3.Arrangement according to claim 1, wherein the switching device isarranged to change state on both positive and negative edges of thefirst clock signal.
 4. Method for determining a first activating pulseedge of a common clock signal wherein the first activating pulse edgeenables a first edge-triggered integrated circuit to receive an inputsignal from at least one second edge-triggered integrated circuit,comprising the steps of:receiving frequency data, in the form of a firstclock signal which is applied to the first integrated circuit and whichhas a lower frequency than the frequency of the common clock signal, ina switching device; receiving the input signal in the switching device;actuating the switching device such that it changes between a first anda second state, based on the first clock signal; when the switchingdevice is in the first state, feeding the input signal through theswitching device to a storage member edge-triggered by the common clocksignal; and when the switching device is in the second state, feedingback an output signal from the storage member through the switchingdevice to the storage member; wherein the output signal from the storagemember is provided to the first edge-triggered integrated circuit.